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application scenarios, the same flow simulator was also used to study geological CO2 storage. Moreover, a new research subject was started in 2021, with the overall
aim of improving an entire simulation ensemble, instead
of individual simulations. The rationale is that there exist similarities between the simulations inside an ensemble, so the numerical successes or failures from the completed simulations can help to improve the upcoming simulations. The current focus is on deriving a quantitative understanding of the level of accuracy in the simulated results. Two journal publications appeared in 2021, one on the numerical and implementational structure of OPM’s flow simulator, the other on a quantitative analysis of the impact of various strategies related to the parallelization of the flow simulator.
Smart Scalable PCI Express
I/O resources like Non-Volatile Memory express11 (NVMe), GPUs, FPGAs are today installed in many modern servers and computers. Today, these resources are only available to applications running on the same server without sub-optimal networks and software. The Smart Scalable PCI Express (PCIe) project’s goal is to solve the network inefficiency and enable servers connected by PCIe Gen4 networks to access remote I/O resources and achieve the same performance as if the I/O devices were local.
In 2021, the project has used the eX3 infrastructure to help prototype an NVMe storage device driver using the Dolphin SmartIO API, which has been developed in conjunction with the Smart Scalable PCI Express project. Although the Device Lending component of SmartIO makes it possible to use existing device drivers, most device drivers are written in a way that assumes exclusive control over the device. Using Device Lending alone, a device may only be used by a single host at the time. To demonstrate software-enabled dis aggregation, we are implementing a distributed NVMe driver. As proof of concept, we have shown that a single NVMe device can be shared and operated by 30 cluster nodes simultaneously, without requiring single root input/output virtualization (SR-IOV) . This driver also demonstrates how multiple sharing aspects of our system may be combined by disaggregating (remote) GPU memory and enabling memory access optimizations.
Advanced HW accelerators for HPC
Compute Express Link (CXL) is one of the proposed next- generation high-speed interconnect buses designed to connect CPUs, memory, and accelerators in servers, data- centres, and computers. The CXL standard is also backed by all the large hardware vendors such as Intel, AMD, ARM, Nvidia, etc.
This project has started investigating the potential of the CXL bus, both as a next-generation replacement for PCI Express and the possibility of using it as a next-generation chip for NUMAScale to connect accelerators, memory, and CPUs in an HPC environment. Activities in this project in 2021 have been preliminary discussions about the possi- bility of the CXL standard for multi-host communication or vendor-specific extensions for adding the functionality in future versions. This work will continue in 2022.
Team Members
Geir Horn
Xing Cai
Tor Skeie
Andreas Thune
Håkon Kvale Stensland Marta Różańska Thomas Hansen
Atle Vesterkjær Einar Rustad Hugo Kohmann
SIRIUS ANNUAL REPORT 2021
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